A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver  

作　　者：郭诗塔 黄鲁 袁海泉 冯立松 刘志明 

机构地区：[1]Department of Electronic Science and Technology,University of Science and Technology of China

出　　处：《Journal of Semiconductors》2010年第3期74-79,共6页半导体学报（英文版）

基　　金：supported by the National High Technology Research and Development Program of China(No.2007AA01Z2b2).

摘　　要：This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal ＆ RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal ＆ RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.

关 键 词：frequency synthesizer dual-modulus prescaler ∑-△ modulator QVCO 

分 类 号：TN74[电子电信—电路与系统] TP332[自动化与计算机技术—计算机系统结构]