A low power 12-b 40-MS/s pipeline ADC  

作　　者：殷秀梅 魏琦 许莱 杨华中 

机构地区：[1]Department of Electronic Engineering,Tsinghua University

出　　处：《Journal of Semiconductors》2010年第3期95-100,共6页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.60976032).

摘　　要：This paper describes a 12-bit, 40-MS/s pipelined A/D converter （ADC） which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers （OTAs） are adopted in all pipeline stages for good power efficiency. In the first two stages, particularly, 3-bit/stage architectures are used to improve the ADC＇s linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.This paper describes a 12-bit, 40-MS/s pipelined A/D converter （ADC） which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers （OTAs） are adopted in all pipeline stages for good power efficiency. In the first two stages, particularly, 3-bit/stage architectures are used to improve the ADC＇s linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.

关 键 词：analog-to-digital converter A/D converter PIPELINE telescope OTA low power high linearity 

分 类 号：TN792[电子电信—电路与系统] TP332[自动化与计算机技术—计算机系统结构]