双电压动态可重构FPGA任务模型及调度算法  

Task scheduling model and algorithm based on dual-Vdd dynamic reconfigurable FPGA

作　　者：徐科君[1] 许文曜[1] 沈继忠[1] 徐新民[1] 

机构地区：[1]浙江大学电子电路与信息系统研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2010年第2期300-304,共5页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(90207002)

摘　　要：通过对单电压动态可重构可编程逻辑门阵列(FPGA)实时任务模型的学习研究,建立基于双电压动态可重构FPGA的非可抢占任务模型.该模型很好地描述了双电压动态可重构FPGA任务的特征,在单电压任务模型的基础上增加了双电压任务模型特有的属性.并基于降序首次自适应算法提出一种新的硬件任务调度算法,该算法在保证任务集限制时间内完成所有任务的同时,利用动态电压调节的方法大幅度减少了任务集完成所需要的能量.在SunSaloris工作站下对任务调度模型及其算法进行仿真和评估,实验数据表明,这种基于双电压的任务模型的调度算法,能够有效降低FPGA任务执行的能耗,对于大规模的任务,能耗最高可节省24.1%.A non-preemptive task model based on dual-supply voltage （Vdd） dynamic reconfigurable field programmable gate array （FPGA） was established by analyzing single voltage reconfigurable FPGA.The model described how the tasks excused in dual-Vdd dynamic reconfigurable FPGA and added special attributes of dual-Vdd task model based on single voltage task model.A novel scheduling strategy was proposed based on the first-fit-decreasing algorithm.The strategy can guarantee the execution deadline of the task set and greatly reduce the execution energy using dynamic adjustment of dual-Vdd.The experiment simulated on Sun Saloris shows that the strategy can achieve the great energy saving,which is up to 24.1% of large task set.

关 键 词：双电压可编程逻辑门阵列 部分动态可重构 硬件任务调度 降序首次自适应算法 

分 类 号：TN432[电子电信—微电子学与固体电子学]