基于FPGA的No.7信令FISU过滤  

No.7 Signaling FISU Filter Based on FPGA

作　　者：罗明阳 廖红云 苏凌旭 

机构地区：[1]重庆金美通信有限责任公司,重庆400030

出　　处：《计算机工程》2010年第6期236-238,共3页Computer Engineering

摘　　要：针对CPU处理填充信号单元(FISU)存在的缺陷,分析No.7信令系统的初始定位和FISU处理过程,提出一种基于FPGA实现FISU过滤的设计方案,给出实现的原理框图、FPGA与CPU之间的通信机制和信号处理流程,使用ISE和ModelSim软件进行仿真。仿真结果表明该方案是正确、可行和有效的。In allusion to the disadvantage of processing Fill-in Signal Unit（FISU） using CPU, on the basis of analyzing the process Of initial aligning and FISU processing in No.7 signaling system, a new design scheme adopting Field-Programmable Gate Array（FPGA） to achieve FISU filter is put forward. The principle figures, communication mechanism between FPGA and CPU, and signal processing flow charts are carried out. ISE and ModelSim software are used to achieve simulation. Simulation result proves that the scheme is correct, feasible and effective.

关 键 词：NO.7信令系统 初始定位过程 填充信号单元过滤 现场可编程门阵列 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]