纳米电路交叉冗余容错技术研究  

Research on Fault-tolerant Techniques Based on Interwoven Redundancy for Nanoscale Circuits

作　　者：张洋[1] 王友仁[1] 张砦[1] 

机构地区：[1]南京航空航天大学自动化学院,江苏南京210016

出　　处：《佳木斯大学学报（自然科学版）》2010年第1期5-8,共4页Journal of Jiamusi University：Natural Science Edition

摘　　要：提出了一种针对纳米电路的数字电路容错设计新方法.该方法基于交叉冗余原理,利用两种二进制错误的不对称性,采用模块化方法对纳米电路进行容错设计.以阵列乘法器为例,采用新方法对电路进行设计和仿真,并结合实验结果与传统的可重构和三模冗余容错方法进行比较.交叉冗余方法无需检测模块及表决器,不会增加系统延时,并且在资源消耗方面远低于传统方法,对纳米电路尤其适用.A new method for designing fault - tolerant digital circuits to reduce the failure rate of nanoscale circuits based on interwoven redundancy and the asymmetric of two kinds of binary errors, using a modular approach to design circuits. With multiplier as an example, this paper conducted a simulation experiment using the new method. The results show that it is better than the traditional fault - tolerant design methods. The new method is especially suitable for nano - circuits because it won＇ t increase the system delay without detection module and voter, and its resource consumption is far less than that of traditional methods.

关 键 词：纳米电路 容错 交叉冗余 可靠性 故障屏蔽 

分 类 号：TN402[电子电信—微电子学与固体电子学]