基于FPGA的NoC验证平台的构建  

Construct NoC validation platform based on FPGA

作　　者：韩高飞[1] 杜慧敏[1] 蒋林[1] 韩俊刚[1,2] 

机构地区：[1]西安邮电学院计算机系,陕西西安710061 [2]西安电子科技大学微电子学院,陕西西安710071

出　　处：《电子设计工程》2010年第3期90-93,共4页Electronic Design Engineering

基　　金：国家863计划项目(2007AA01Z111);国家自然科学基金资助项目(60976020)

摘　　要：针对基于软件仿真片上网络NoC(Network on Chip)效率低的问题,提出基于FPGA的NoC验证平台构建方案。该平台集成可重用的流量产生器TG(Traffic Generation),流量接收器TR(Traffic Receiver)以及NoC软件,用于对NoC原型系统进行功能验证和性能评估。实际设计一个多核NoC,并用该平台对其进行FPGA验证,结果表明该平台的验证速度比软件仿真提高16 000倍以上,并能对多种不同结构、路由算法、流控策略的NoC进行功能验证和性能评估。To solve the problem of Network on Chip （NoC） low efficiency based on software simulation,a FPGA based validation platform construction scheme for Network on Chip （NoC）was proposed.This platform intergrates reusable modules of a traffic generation （TG）, a traffic receiver （TR） and a NoC software, which are used to accomplish the function validation and performance evaluation.A NoC comprises many switching nodes was designed,and the NoC was validated by this plat- form.The experimental result shows that the speed of this platform reaches over 16000 times faster than software simulation; meanwhile, it can work on NoC which has different topology structure, routing algorithm and flow control strategy.

关 键 词：片上网络(NoC) 可重用 FPGA 验证平台 

分 类 号：TP393.02[自动化与计算机技术—计算机应用技术]