基于FPGA的差分信号阻抗匹配研究  

Research of impedance matching about differential signal based on FPGA

作　　者：曾晶[1] 唐湘成[1] 王德胜[1] 

机构地区：[1]西南技术物理研究所,四川成都610041

出　　处：《电子设计工程》2010年第3期121-123,共3页Electronic Design Engineering

摘　　要：为了节约PCB板空间,充分灵活利用FPGA内部资源,对FPGA内置差分信号匹配终端进行研究。根据差分信号阻抗匹配的基础理论,在自制的PCB电路板上利用差分信号线传递时钟和图像数据。在FPGA内设置不同类型的片内匹配终端,通过示波器观察时钟、图像数据,利用Visual DSP++软件自带的Image Viewer功能观察图像。结果表明,使用片内匹配终端不会恶化差分信号,并能大大节省PCB板空间,且终端匹配更灵活。In order to save PCB board space,fully flexible use of FPGA intemal resources,it did some research about the terminal in the FPGA which was used to match the differential signal.According to the basic theory about impedance matching of differential signal,the clock and image data by differential signal line in the self-made PCB circuit board was transmitted.The different OCT （on-chip termination）was set in FPGA,and the clock and image data signals through the oscilloscope was observed the image by Image Viewer tool in Visual DSP＋＋ was also observed.The results show that the use of onchip differential signal matched termination does not deteriorate dofferential signal,greatly reduces PCB board space,and makes the matching about terminal more flexible.

关 键 词：差分信号 阻抗匹配 片内匹配终端(OCT) FPGA 

分 类 号：TN47[电子电信—微电子学与固体电子学]