一种高增益低功耗的CMOS低噪声放大器  

A Low-Power and High-Gain CMOS Low Noise Amplifier

作　　者：康劲[1] 孙玲玲[1] 文进才[1] 赵明付[1] 章少杰[1] 

机构地区：[1]杭州电子科技大学射频电路与系统教育部重点实验室,杭州310018

出　　处：《电子器件》2010年第1期37-40,共4页Chinese Journal of Electron Devices

基　　金：国家自然科学基金资助(60601021);长三角科技合作项目资助(08515810103;2008C16017)

摘　　要：设计了一种新型的全集成的电流复用两级共源低噪声放大器,采用新型输入匹配和一个级联的级间谐振电感实现了低功耗高增益。为了降低芯片面积,两个LC并联网络代替了传统的大电感。这种新型的电流复用结构更有利于输入匹配,降低噪声和功耗。采用SMIC0.18μm RF CMOS工艺制作了一个频率为2.4GHz,噪声系数1.7dB,S11为-30dB,S22为-36dB,功率增益为23dB,反向隔离度小于-35dB,在1.8V的供电电压下仅消耗2mA。A current-reused two-stage low noise amplifier （LNA） topology is investigated in this paper, which adopts a newly architecture for input matching and a series inter-stage resonance. To save the chip area, two LC network was used instead of the large gate inductor Lg and the load inductor of the first stage. The characteristics of the series inter-stage resonance in gain enhancement are also analyzed. The proposed 2.4 GHz LNA is implemented based on a 0. 18 μm CMOS technology. Simulation results show power gain = 23 dB, NF = 1.7 dB, S11= 30 dB, S22 = -36 dB and the reverse isolation better than 35 dB, while drawing 2 mA current from a 1.8 V voltage supply.

关 键 词：CMOS 输入阻抗匹配 级间匹配 电流复用 低噪声放大器 

分 类 号：TN4[电子电信—微电子学与固体电子学]