电流模PWM降压DC_DC片内补偿电路的设计实现  

The Design and Realization of Internal Compensation Circuit for Current-Mode PWM Step-Down DC_DC Converters

作　　者：代国定[1] 徐洋[1] 李卫敏[1] 胡波[1] 

机构地区：[1]西安电子科技大学超高速电路设计与电磁兼容教育部重点实验室,西安710071

出　　处：《电子器件》2010年第1期53-57,共5页Chinese Journal of Electron Devices

基　　金：国家部委预研基金资助(9140A08010208DZ0123);西安应用材料创新基金资助(XA-AM-200817)

摘　　要：对单片电流模降压DC_DC的内部电流环与电压环的稳定性进行了分析研究,分别采用分段线性斜坡补偿与内置频率补偿技术,有效消除环路亚谐波振荡并克服了稳定性对输出负载以及误差放大器增益的依赖,提高了芯片的瞬态响应速度及输出带负载能力。采用TSMC0.25μmBCD工艺设计实现了一款高电压电流模PWM降压型的DC_DC芯片,spectre仿真结果表明,输出电流可达2A,其线性调整率和负载调整率均小于0.3%,输出电压对负载1A时的阶跃响应时间小于70μs。The stabilities of the internal current loop and voltage loop in a current-mode PWM step-down DC_DC are both analyzed and researched in this paper. The piecewise-linear slope compensation technology and built-in frequency compensation technology are adopted which not only avoid the loop＇s sub-harmonic oscillation efficiently, overcome the stability of the output depending on load and the error amplifier gain, but also rise the speed of system＇s transient response and enhance the load capacity of the chip＇s output. A high voltage current-mode PWM step-down DC_DC is designed by TSMC 0.25μm BCD process and simulated in spectre. The results indicate that output current is up to 2 A, both linear and load regulation are less than 0.3 %, and the output voltage can recover within 70 μs for 1 A load step.

关 键 词：降压型DC_DC 电流模PWM 分段线性斜坡补偿 频率补偿 环路增益 

分 类 号：TN432[电子电信—微电子学与固体电子学]