连续时间型ΣΔ调制器的系统级设计和建模方法  

System-level Design and Modeling of a Continuous-time ΣΔ Modulator

作　　者：张翼[1] 叶天凤[1] 洪志良[1] 刘洋 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203 [2]美国模拟器件公司上海设计中心,上海200021

出　　处：《固体电子学研究与进展》2010年第1期102-107,158,共7页Research & Progress of SSE

基　　金：国家863计划项目(SQ2008AA01ZX1480432);美国模拟器件公司资助项目

摘　　要：采用冲激不变法把z域环路滤波器变换到s域,并对连续时间型ΣΔ调制器设计中的非理想因素进行系统级建模和仿真。基于低功耗设计考虑,调制器采用有源-无源混合型环路滤波器,并通过离散时间微分技术移除信号求和模块。设计实例实现了一个五阶3-bit连续时间型ΣΔ调制器,采用SMIC0.18μm1P6M标准CMOS工艺验证。芯片工作在1.8V电源电压和128MHz时钟频率,在1MHz的信号带宽内,调制器的动态范围为84dB,峰值SNR和SNDR分别为80dB和78dB,功耗为9mW。测试结果验证了设计技术和建模方法。Impulse Invariant Transformation is used to transform the loop filter from z-domain to s-domain. Non-idealities of the continuous-time ∑△ modulator are system-level modeled and simulated. Based on low power design consideration, a hybrid active-passive loop filter is employed and the signal summing block is removed by using discrete-time differentiation technique. A 5th-order, 3-bit continuous-time EA modulator is taken as a design example. The chip is fabri- cated in SMIC 0. 18 μm 1P6M CMOS technology. The experimental results show that it achieves peak SNR of 80 dB, peak SNDR of 78 dB and dynamic range of 84 dB over a 1 MHz signal band- width when clocked at 128 MHz. It dissipates 9 mW from a 1.8 V supply. The design example has verified the design methodology.

关 键 词：冲激不变法 连续时间 ∑△调制器 低功耗设计 

分 类 号：TN761[电子电信—电路与系统]