一种基于FPGA的高精度大动态数字延迟单元的设计  

A Design of Digital Delay Line Based on FPGA

作　　者：刘鹏[1,2] 许可[2] 

机构地区：[1]中国科学院研究生院,北京100190 [2]中国科学院空间科学与应用研究中心,北京100190

出　　处：《微计算机信息》2010年第8期132-134,共3页Control & Automation

摘　　要：本文提出了一种数字延迟单元的设计方案,该方案能够实现0.1ns的延迟度精度和10ms的动态范围,通过调节该方案的工作参数可以很方便的实现更大的动态范围。该电路在Virtex5系列的FPGA上实现,其核心由粗延时单元和精延时单元两部分组成,粗延时单元采用计数器法实现,精延时单元的核心由IODELAY基元构成,语言代码通过了FPGAdv软件的综合和仿真。目前该单元电路已成功的应用在卫星雷达高度计的地面回波模拟器上。The design of a new digital delay line（DDL） is introduced in this paper.This DDL can achieve the time delay by the step of 0.1ns, and the delay duration can be easily expanded to more than 10ms in this scheme.The delay circuit was constituted by a wide delay unit and a narrow delay unit.The wide delay unit was build up by user-defined counters, while the narrow delay unit make up of an IODELAY unit.Its designed code has been compiled and simulated on FPGAdv software.It had been applied to control the delay of the radar signal envelop in radar altimeter simulator successfully.

关 键 词：数字延迟线 FPGA IODELAY 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]