乘法器复用技术在滑窗FIR滤波处理中的运用  

The Application of the Multiplier Reused Technique for Slip-Window FIR Filter Processing

作　　者：陈风波[1] 董奇才 李念军[3] 鲍振[1] 

机构地区：[1]空军雷达学院信息与指挥自动化系,武汉430019 [2]第二炮兵士官学校通信工程系,青州262500 [3]武汉邮电科学研究院,武汉430074

出　　处：《微计算机信息》2010年第8期140-141,19,共3页Control & Automation

摘　　要：随着超大规模集成电路的飞速发展,FPGA集成的硬件乘法器越来越多,内核时钟越来越快,使得FPGA在实时信号处理中得到广泛应用。介绍了FIR滤波运算的原理与硬件处理结构,通过乘法器的复用技术,解决了实现滑窗FIR滤波处理时,FPGA内部乘法器的高速运算与外部慢速数据率之间的矛盾。With the fast development of the super scale IC, the hardware multipliers integrated in FPGA is more and the core clock is faster, which make FPGA applied widely in real-time signal processing.The operating principle and hardware processing structure of FIR is introduced.By using the multiplier reused technique, the contradiction between the inner high-speed operation and the outside slow data rate in the slip-window FIR processing with FPGA is solved.

关 键 词：滑窗FIR滤波 实时信号处理 乘法器复用 数据率 

分 类 号：TN911[电子电信—通信与信息系统]