一种高速实时浮点蝶形运算单元的设计与实现  

Design and implementation of high-speed and real-time floating-point butterfly unit

作　　者：杨军[1] 郭跃东[1] 丁俊[1] 

机构地区：[1]云南大学信息学院,昆明650091

出　　处：《仪器仪表学报》2010年第3期519-524,共6页Chinese Journal of Scientific Instrument

基　　金：云南省教育厅科学研究基金重点项目(09C0011)资助

摘　　要：本文以CORDIC算法为基础,将浮点数的复乘与旋转因子的求值都统一到了一个迭代运算中。既减少了复乘运算的复杂度也降低了快速傅里叶变换中蝶形单元在处理浮点数时的难度,成为浮点FFT处理器设计的一种新思路。该蝶形运算单元不受外部存储器的大小,可以处理高样本数的傅里叶变换,同时具有处理范围大,处理精度高的特点。最终以Altera的EP2C20F484C6芯片为下载目标,其时序仿真可正常运行在100 MHz的时钟频率下。An innovation design method of high-speed and real-time floating-point butterfly unit is put forward in this paper.It is based on CORDIC algorithm and is fully IEEE 754 compliant.The design uses an iterative computation process instead of two computation processes,which are the complex multiplication and the evaluation of trigonometric function.The butterfly unit is not restricted by the external memory size,so it can handle large quantity of data,and has the features of large input scope and high-precision operation.Finally,we made a timing simulation using an Altera＇s chip of EP2C20F484C6,which can run correctly under 100 MHz system clock.

关 键 词：蝶形运算 浮点 CORDIC算法 FPGA 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]