AVS分数像素插值算法的VLSI实现  

VLSI implementation of sub-pixel interpolation algorithm for AVS

作　　者：王方晴[1] 王祖强[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电子技术应用》2010年第4期44-47,共4页Application of Electronic Technique

摘　　要：基于AVS运动补偿分数像素插值算法,提出了一种新的VLSI结构,满足了AVS基准档次6.2级别(1920×1080,4:2:2,30f/s)高清视频实时解码的要求。介绍了AVS分数像素插值算法,采用一种新的基于移位寄存器的寄存器文件作为内部像素存储器,提高了并行处理效率,并将脉动阵列应用到AVS插值滤波器中,有效提高了运动补偿插值运算的速度。This paper proposed to give a new VLSI architecture of sub-pixel interpolation algorithm in motion compensation which based on the AVS（audio video coding） standard. This architecture can support real-time motion compensation of AVS profile 6.2 level （1920×1080,4：2：2,30 f/s）. This paper describes the sub-pixel interpolation algorithm for AVS, proposes a new architecture of inner pixel memory based on shift registers to enhance efficiency of parallel processing. Moreover, tile systolic array is applied to implementation of AVS interpolation filter, which effectively improves the performance of interpolation in motion compensation.

关 键 词：AVS 像素插值 并行处理 脉动阵列 

分 类 号：TN919.8[电子电信—通信与信息系统]