Low power CMOS preamplifier for neural recording applications  

作　　者：张旭 裴为华 黄北举 陈弘达 

机构地区：[1]State Key Laboratory for Integrated Optoelectronics,Institute of Semiconductors,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2010年第4期62-67,共6页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.60776024,60877035,60976026,90820002);the National High Technology Research and Development Program of China(Nos.2007AA04Z329,2007AA04Z254).

摘　　要：A fully-differential bandpass CMOS （complementary metal oxide semiconductor） preamplifier for extra- cellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.A fully-differential bandpass CMOS （complementary metal oxide semiconductor） preamplifier for extra- cellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.

关 键 词：neural signal amplifier low noise low power subthreshold circuit design 

分 类 号：TN722.71[电子电信—电路与系统]