A high speed sampler for sub-sampling IR-UWB receiver  

作　　者：邵轲 陆波 夏玲琍 洪志良 

机构地区：[1]State Key Laboratory of ASIC and System,Fudan University

出　　处：《Journal of Semiconductors》2010年第4期72-75,共4页半导体学报（英文版）

基　　金：supported by the National High Technology Research and Development Program of China(No.2009AA01Z261);the State Key Laboratory of Wireless Telecommunication,Southeast University.

摘　　要：A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.

关 键 词：IR-UWB SAMPLER sub-sampling TH clock generator 

分 类 号：TN851[电子电信—信息与通信工程]