高速ATM中CRC算法与信元定界的FPGA实现  

FPGA Implementation of CRC Algorithm and Cell Delineation in High-speed ATM

作　　者：张惠峥[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081

出　　处：《无线电通信技术》2010年第2期46-49,共4页Radio Communications Technology

摘　　要：在通信领域循环冗余码CRC得到了广泛的应用。为解决高速ATM中信头误码差错控制和信元定界问题,通过对循环冗余校验原理的分析,采用递推的方法得出了一种高效的CRC算法。该算法能检测到多个bit错误,并能纠正单bit的错误。相对于一般的按位串行计算或者查表并行计算的方法,这种算法运算速度快且不需要额外的空间存储余数表,提高了高速链路上数据吞吐率。数据之间逻辑关系简单,十分便于采用FPGA实现。The cyclic redundancy codes are applied widely in the field of telecommunications.To implement the header error control and cell delineation in high-speed ATM, this paper puts forward an effective parallel CRC algorithm by using the recursion method based on the theory of cyclic redundancy checkout.This algorithm can not only detect multi-bit error but also correct single-bit error.Differing from general serial algorithm or the parallel algorithm based on list-checking, it is faster and doesn’t need the extra memory space to store the remainder list, and improves dramatically the data throughput of higher-speed lines.The logic relationship of data is simple, and it is very easy to be implemented by FPGA.

关 键 词：循环冗余码 信元定界 并行处理 

分 类 号：TN913[电子电信—通信与信息系统]