循环冗余校验(CRC)编码器设计及FPGA实现  

Design and FPGA Implement of Cyclic Redundancy Check(CRC)Encoder

作　　者：许正荣[1] 贾贤龙[2] 杨敦毅[1] 

机构地区：[1]安徽农业大学信息与计算机学院,安徽合肥230036 [2]合肥工业大学,安徽合肥230009

出　　处：《安徽农业科学》2010年第8期4355-4357,共3页Journal of Anhui Agricultural Sciences

基　　金：安徽省高校青年教师资助项目(2007jq1047);安徽省省级一般项目(KJ2008B028)

摘　　要：介绍了循环冗余校验(CRC)编码器的设计及FPGA实现过程,采用原理图输入法对整个系统进行了编译和仿真,并在芯片EP1K30TC144-3中对该设计的核心部分进行了测试验证。结果表明,试验数据与理论分析结果完全相符。The process of design and FPGA implement of cyclic redundancy check（CRC） encoder was introduced.The whole system was compiled and emulated with schematic diagram input method,and the core part of the design was tested and verified in chip of EP1K30TC144-3.The results showed that the tested data was completely conformed（ with the theoretical analysis results.

关 键 词：循环冗余校验(CRC) 原理图输入 现场可编程门列阵(FPGA) 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]