基于功耗优化的流水线ADC研制  

Power Optimization Design and Fabrication of Pipelined ADC

作　　者：卫宝跃[1] 周玉梅[1] 范军[1] 胡晓宇[1] 陈利杰[1] 

机构地区：[1]中国科学院微电子研究所专用集成电路设计实验室,北京100029

出　　处：《半导体技术》2010年第4期403-406,共4页Semiconductor Technology

基　　金：国家自然科学基金(60676015)

摘　　要：提出了一种使流水线模数转换器功耗最优的系统划分方法。采用Matlab进行模拟,以信噪比(SNR)为约束,得出一定精度条件下,流水线ADC各子级分辨率和各级采样电容缩减因子的不同选取组合;又以功耗为约束,从以上多种组合中找到满足最低功耗的流水线ADC结构划分方法。基于以上分析,在SMIC 0.35μm工艺条件下,设计了一个10 bit、采样率20 MS/s的流水线ADC,并流片验证。2.1 MHz输入频率下测试,SFDR=73 dB、ENOB=9.18 bit,模拟部分核心功耗102.3 mW。An arithmetic is advanced with the goal of minimizing power dissipation in pipelined ADC. Analyzing with Matlab, multiple choices between the resolution per sub-stage and the scaling factor of capacitor size in pipelined ADC is obtained, under the signal to noise rate （ SNR ） restriction in certain resolution. Under the power restriction, a pipelined ADC structure dividing method with lowest power Consumption was chosen in the discussion choices above. A 10 bit, 20 MS/s pipelined ADC was designed and taped out with the power optimization results in SMIC 0.35 μm CMOS process. The results show that at 2.1 MHz input signal, SFDR is 73 dB, ENOB is 9.18 bit, power dissipates is 102.3 mW

关 键 词：功耗优化 电容缩减因子 子分辨率 流水线 

分 类 号：TN432[电子电信—微电子学与固体电子学]