SoC的可靠性和低功耗协同优化  

Reliability and Power Consumption Optimization for SoC

作　　者：张小林[1,2] 杨根庆[1] 张宇宁[1,2] 

机构地区：[1]中国科学院上海微系统与信息技术研究所,上海200050 [2]中国科学院研究生院,北京100039

出　　处：《西南交通大学学报》2010年第2期284-289,共6页Journal of Southwest Jiaotong University

基　　金：国家863计划资助项目(2006AA01Z216);上海市科委国际合作资助课题(052207046)

摘　　要：针对SoC的高可靠性和低功耗的设计要求,分析了动态电压与频率调节技术对系统功耗、温度和软错误率的影响,构建了SoC的可靠性和功耗的协同优化设计模型,提出了可靠性和低功耗协同设计的新方法,并通过考虑可靠性的动态电压与频率调节调度算法进行了仿真,验证了算法的有效性和可行性.结果表明,在可靠性降低5%的情况下,可节省约15.99%的功耗.Tradeoff between the high reliability and low power consumption for SoC（system on a chip） was investigated.Based on the proposed reliability and power consumption characterization model,reliability-aware and low-power design was illustrated as a design methodology to balance reliability enhancement and power reduction.Reliability-aware dynamic voltage/frequency scheduling（DVFS） algorithm was demonstrated as a case study of this new design methodology.The simulation demonstrates the effectiveness and feasibility of the methodology and obtains a significant improvement of 15.99% in energy consumption at a cost of 5% reliability decrease.

关 键 词：动态电压与频率调节 可靠性 低功耗 片上系统 

分 类 号：TP302.9[自动化与计算机技术—计算机系统结构]