并行分时流水线A/D转换器系统级研究  

Study on Architecture of Parallel Pipelined A/D Converter

作　　者：王友华[1,2] 张俊安[1,2] 余金山[1,2] 王永禄[1,2] 

机构地区：[1]模拟集成电路国家级重点实验室,重庆400060 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2010年第2期165-168,共4页Microelectronics

基　　金：模拟集成电路国家级重点实验室基金资助项目(9140C0901080802);国家自然科学基金资助项目(60906009);中国博士后科学基金资助项目(20090451423)

摘　　要：基于并行分时A/D转换器的理论研究,对该类型A/D转换器进行了系统行为级设计和仿真。分析了系统中并行误差及流水线A/D转换器等误差源对整个系统性能的影响。通过计算机仿真,给出了系统模块的设计参数。通过理论分析与系统仿真,为并行分时流水线A/D转换器的设计提供了理论依据和数据参考,为该类型A/D转换器提供了设计优化方向。The architecture of parallel pipelined A/D converter was studied. Non ideal sources of the parallel pipelined A/D converter were analyzed and modeled. Degradation of system performance caused by these non-ideal sources was simulated. Based on theoretical analysis and simulation, key specifications of the main functional blocks of parallel pipelined A/D converter were provided. This work could be used as a good guidance for designing parallel pipelined A/D converter.

关 键 词：并行分时流水线 A/D转换器 系统建模 

分 类 号：TN792[电子电信—电路与系统]