一种Σ-△A/D转换器抽取滤波器的设计  

Design of Decimation Filter for Sigma-Delta A/D Converter

作　　者：吴倩瑜[1,2] 张正璠[2,3] 李儒章[2,3] 石立春[2,4] 

机构地区：[1]重庆大学光电工程学院,重庆400044 [2]模拟集成电路国家级重点实验室,重庆400060 [3]中国电子科技集团公司第二十四研究所,重庆400060 [4]西安电子科技大学微电子学院,西安710071

出　　处：《微电子学》2010年第2期173-176,共4页Microelectronics

摘　　要：设计了一种Σ-ΔA/D转换器中的数字抽取滤波器。该滤波器应用于音频范围,采用多级多采样率的结构,由梳状滤波器、补偿滤波器以及两个半带滤波器组成。滤波器系数用标准符号编码实现,减少了乘法单元的使用。采用Simulink模拟过采样128倍的4位调制器输出;用Verilog编写用于测试的滤波器代码。在Matlab中分析滤波器输出码流,得到的信噪比为101 dB,能够满足高端音频A/D转换器的要求。A digital decimation filter in E-A A/D converter for audio applications was designed. The filter has a multistage and multi-rate structure consisting of a cascaded-integrator-comb （CIC） filter, a compensation filter and two half-band filters. To reduce the number of multiplication units, coefficients of the filter were encoded by canonical-signed digital （CSD）. Filter code for testing was written in Verilog, and output of the 128-time oversampling 4- bit modulator was simulated with Simulink. Results showed that the filter had an SNR of 101 dB, which is suitable for high-end audio applications.

关 键 词：A/D转换器 数字抽取滤波器 标准符号编码 级联梳状滤波器 

分 类 号：TN713[电子电信—电路与系统]