数字电视调谐器中锁相环锁定时间的计算  

Calculation Method for Locking Time of PLL in DTV Tuner

作　　者：吴秀龙[1,2] 吉新春[1] 吴建辉[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096 [2]安徽大学电子科学与技术学院,合肥230039

出　　处：《微电子学》2010年第2期209-211,216,共4页Microelectronics

基　　金：国家高技术发展研究(863)计划基金资助项目(2007AA01Z280);中国博士后科学基金资助项目(20090450071)

摘　　要：对数字有线电视调谐器中带有源滤波器结构的锁相环进行分析,深入研究了锁定时间与环路参数的关系,在推导环路相位误差的基础上,提出了一种计算环路锁定时间的方法,并给出具体的计算公式。计算结果与仿真/测试结果比较吻合,说明得到的公式能准确计算出锁定时间,而且可以直观地反映锁定时间与环路参数之间的关系。PLL with active filter for DTV tuner was analyzed. The relationship between locking time and loop parameters was discussed. A method for calculating locking time was presented based on derivation of phase error. Calculated results were in good agreement with simulated and test results. With formulas derived, which directly re-flect the relationship between locking time and loop parameters, locking time can be accurately worked out,

关 键 词：数字调谐器 锁相环 锁定时间 相位误差 

分 类 号：TN911.8[电子电信—通信与信息系统]