基于跳跃访问控制的低功耗分支目标缓冲器设计  

Low Power Branch Target Buffer Design Based on Hopping Access

作　　者：喻明艳[1] 张祥建[1] 杨兵[1] 

机构地区：[1]哈尔滨工业大学微电子中心,哈尔滨150001

出　　处：《计算机辅助设计与图形学学报》2010年第4期695-702,共8页Journal of Computer-Aided Design & Computer Graphics

摘　　要：传统的分支目标缓冲器(BTB)每个取指周期都要进行访问,由于程序中的分支指令只占总指令数的20%左右,使得大约80%的BTB访问都是无效的.为此,利用程序控制流中分支指令间距固定的特性,提出一种对性能影响极小的BTB跳跃访问算法.在BTB中存储分支指令到运行路径中下一条分支指令的距离,BTB命中后,根据相应的分支距离来关闭当前分支指令与下一条分支指令之间的BTB访问,以有效地提高访问效率并降低动态功耗.该算法在嵌入式处理器中实现时只控制预测跳转分支指令的BTB跳跃访问,减少了硬件资源的开销.在硬件模型上进行模拟和综合后的结果表明,在128分支项的BTB中,采用文中算法可以降低72%的动态功耗,而性能损失仅为0.013%.The traditional branch target buffer （BTB） has to be always accessed during instruction fetch stage. Since the branch instructions account for about 20% of the total executed instructions, at least 80% of the BTB accesses are redundant. Considering the characteristic of the fixed distance of branch instructions, we proposed a hopping access （HA） algorithm, by which we reduced the accesses to the BTB to achieve a significant dynamic energy reduction while maintaining the performance. By performing HA algorithm the branch distances between two consecutive branch instructions are dynamically computed and updated into the according BTB entries during program execution. When BTB hits, the BTB accesses are skipped until next branch according to the relevant branch distance. The algorithm is only applied to the predicted taken branches to reduce the overall hardware overhead. Experimental results on the hardware model shows that HA algorithm achieves a 72 % dynamic energy reduction over a 128-entry BTB at the cost of a negligible 0.013%performance loss.

关 键 词：分支目标缓冲器 分支预测器 低功耗 嵌入式处理器 硬件模型 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]