Turbo编码的并行设计与优化  

Parallel Turbo Coding Technology and Optimization

作　　者：曾健平[1] 张亦驰[1] 李玉国[1] 

机构地区：[1]湖南大学物理与微电子科学学院,长沙410082

出　　处：《宇航计测技术》2010年第2期75-78,67,共5页Journal of Astronautic Metrology and Measurement

摘　　要：提出了一种基于3GPP TS 25.212协议的单RAM的turbo并行编码技术,并详细介绍了所设计tur-bo并行编码器硬件结构框架的具体实现方法及优化方式,解决了传统编码技术中的低速和芯片面积过大的问题,使其适应当今通信系统。该编码技术计算S序列时,并不直接计算基序列,而使用中间序列的计算来代替,极大的减少了计算的周期,减少了芯片的使用面积。Matlab的仿真结果表明,该设计在码片速率为61.44 MHz时,编码速率达到了0.35 ms,满足通信系统的高速传输要求。A protocol based on 3GPP TS 25. 212 Single-RAM parallel turbo coding techniques is presents, and detailed description of the design of parallel turbo encoder hardware architecture framework and optimization methods are introduced. The problem that traditional coding techniques in low-speed and chip area is too large to adapt to today＇s communication systems is resolved. The coding technology, computing S sequence is not directly calculates the base sequence of calculations used to replace the middle sequence, which greatly reduces the calculation cycle. Matlab simulation results show that when the design in the chip rate of 61.44 MHz, the code rate reached 0.35 ms, high-speed communications systems to meet the transmission requirements.

关 键 词：TURBO 并行编码 计算方法 设计 优化 

分 类 号：TN492[电子电信—微电子学与固体电子学]