基于ACE约束的S-IRA编译码器设计  

Design of S-IRA Code Encoder and Decoder with ACE Constrained

作　　者：刘朋利[1] 何欢[2] 

机构地区：[1]解放军理工大学通信工程学院研究生3队,江苏南京210007 [2]解放军理工大学通信工程学院研究生1队,江苏南京210007

出　　处：《山西电子技术》2010年第2期47-49,63,共4页Shanxi Electronic Technology

摘　　要：考虑到结构化非规则重复累积码具有准循环的结构便于硬件实现,采用了结构化非规则重复累积码进行编码器设计。准循环矩阵的构造采用了基于ACE约束的PEG填充构造方法。结合所用码型的特点,设计出了简单有效的编码流程图。译码方面,采用了分层修正最小和译码算法,并设计出了译码器结构。Motivated by the Quasi-cyclic structure and low complexity implement of hardware of S-IRA code,the encoder is designed based on it.The QC-Check matrix is designed with PEG algorithm of generalized ACE constrained.The structure of encoder is proposed concerning with the code used.A novel decoder architecture based on LMMSA decoding algorithm is also proposed and elaborated in this paper.

关 键 词：结构化非规则重复累积码 分层修正最小和译码算法 编码器结构 译码器结构 

分 类 号：TN911.22[电子电信—通信与信息系统]