一种能够实现多种散列函数的VLSI-IP模块设计  

A VLSI-IP Module Design for Implementing Multi-hash Function

作　　者：陈英杰[1] 王海欣[1] 白国强[1] 陈弘毅[1] 

机构地区：[1]清华大学微电子研究所,北京100084

出　　处：《微电子学与计算机》2010年第4期89-94,共6页Microelectronics & Computer

基　　金：国家自然科学基金项目(60576027);国家"八六三"计划项目(2006AA01Z415)

摘　　要：给出了一种能够实现多种散列函数的VLSI-IP模块设计,应用到一种网络安全处理器的认证模块设计中.在实现SHA-1和CHI安全散列函数运算的基础上,进而利用迭代技术实现散列消息鉴别码HMAC-SHA-1和HMAC-CHI-160,并生成SSL(Security Socket Layer)协议中所需的主密钥和密钥块.采用SMIC0.13μm CMOS工艺,综合后关键路径为4.56ns,面积为0.61mm2,运算SHA-1的吞吐率达到1.82Gb/s.This work presents a VLSI-IP module design for implementing multi-hash function, applied to an authentication module design for network security processor. On the basis of implementing hash function such as SHA-1 and CHI, by using iteration technology, this module supports not only keyed-hashing for message authentication such as HMAC-SHA-1 and HMAC-CHI-160,but also generating MASTER-KEY and KEY-BLOCK in SSL（Security Socket Layer） protocol. This module was designed with SMIC 0.13μm CMOS technology occuping 0.61mm2 with critical path of 4.56ns, the implementation result gives a throughput of 1.82Gb/s for SHA-1.

关 键 词：网络安全处理器 散列函数 散列消息鉴别码 主密钥 密钥块 迭代 

分 类 号：TN918[电子电信—通信与信息系统]