基于HLS技术的Rijndael算法IP核实现与优化  

Implementation and Optimization of Rijndael Arithmetic IP Core Based on HLS Technology

作　　者：孙桂玲[1] 纪永鑫[1] 张潺潺[1] 李维祥[1] 

机构地区：[1]南开大学信息技术与科学学院,天津300071

出　　处：《微电子学与计算机》2010年第4期205-208,212,共5页Microelectronics & Computer

基　　金：国家"八六三"计划项目(2006AA01Z217);天津市科技支撑计划重点项目(08ZCKFGX00500)

摘　　要：为了降低传统设计模式在应对大规模SoC设计时带来高复杂度,使用高层次综合HLS技术进行了Rijndael算法IP核的设计、综合与仿真.针对Rijndael算法中的多种运算模块,研究并设计了面向硬件的编码方式及优化方案.通过对比,使用高层次综合技术设计的IP核在各方面都接近或超越了使用传统方式设计的IP核,而设计复杂度大大降低,证明了使用HLS方法进行设计的优越性.In order to reduce the high complexity of the traditional SoC design method, this paper presents the design, synthesis and simulation flow of the Rijndael arithmetic IP Core using high level synthesis （HLS） technology. A hardware-oriented coding style and its optimization scheme specifically for the Rijndael arithmetic is also studied and designed. Through a comparison with a traditionally designed IP Core, the IP Core designed by HLS technology outperforms in nearly all respects, with a significantly reduced design complexity, which greatly proves the advantage of HLS.

关 键 词：高层次综合 Catapult SYNTHESIS RIJNDAEL SYSTEMC 

分 类 号：TN47[电子电信—微电子学与固体电子学]