时钟低摆幅三值双边沿低功耗触发器的设计  

Design of Low-Swing Clock Ternary Low Power Double Edge-Triggered Flip-Flop

作　　者：曾小旁[1] 汪鹏君[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《华东理工大学学报（自然科学版）》2010年第2期279-283,共5页Journal of East China University of Science and Technology

基　　金：国家自然科学基金项目(60776022);浙江省科技计划项目(2008C21166);宁波大学教授基金项目

摘　　要：通过对各类多值触发器的研究,提出了一种反馈保持型时钟低摆幅三值双边沿低功耗新型触发器(Feedback Keeper Low-swing Clock Ternary Low-Power Double-Edge-Triggered Flip-Flop,FK-LSCTLPDFF)设计方案。该方案利用反馈保持避免电路因输入信号瞬间毛刺引起的错误翻转,利用时钟信号双边沿跳变敏感抑制冗余跳变,利用时钟低摆幅降低三值触发器功耗。该电路与三值单边沿触发器相比,在保持相同数据吞吐量的条件下,可使时钟信号的频率减半,从而降低整个电路的系统功耗。通过PSPCIE模拟,验证了所设计电路具有正确逻辑功能,低功耗特性明显。By analyzing the existing multiple-value flip-flop,this paper proposes a novel design scheme of feedback-keeper low-swing clock ternary low-power double edge triggered flip-flop（FK-LSCTLPDFF）.The proposed flip-flop avoids the incorrect shift caused by the input pulse by using the feedback-deeper.In a TDETFF,both the rising and falling edges of the clock signal are used to transfer data from input to output so as to restrain the redundancy of the clock signal.In this way,for a given throughput,the clock frequency can be halved with respect to a system by using ternary single-edge triggered flip-flop（TSETFF）,with a reduction of power dissipation.Finally,the PSPICE simulation results indicate that the novel scheme has correct logic function and the character of clearly low power.

关 键 词：多值逻辑 触发器 时钟低摆幅 低功耗设计 

分 类 号：TN432[电子电信—微电子学与固体电子学]