AHB-Wishbone总线桥的设计与实现  

Design and Reseach of AHB-Wishbone Bus Bridge

作　　者：万静[1] 王宏滨[1] 

机构地区：[1]哈尔滨理工大学计算机科学与技术学院,黑龙江哈尔滨150080

出　　处：《自动化技术与应用》2010年第2期54-57,共4页Techniques of Automation and Applications

摘　　要：为了实现SOC中集成在不同总线上的IP之间进行有效的通信,通过比较AHB总线和Wishbone总线的协议,本文提出了一种基于有限状态机的AHB-Wishbone总线桥的设计,并使用System Verilog语言实现。设计结果通过在ModelSim工具下的功能仿真,表明该总线桥符合片上总线转换的要求。In order to achieve communication between different IPs which integrated on different buses of the SOC,through compare AHB bus protocol with Wishbone bus protocol,the paper introduces a design model of AHB-Wishbone bus bridge based on finish state machine,by using System Verilog language.The implementation of passed function simu-lation by ModelSim indicates that the bus bridge meets the requirement of On-Chip bus conversion.

关 键 词：AHB总线 WISHBONE总线 总线桥 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]