基于FPGA的CPU多MII通信接口实现  

FPGA Based Implementation of the Communication Interface between CPU and Multi-MII

作　　者：郁专[1] 王兵[1] 武杰[1] 

机构地区：[1]中国科学技术大学近代物理系,安徽合肥230026

出　　处：《核电子学与探测技术》2010年第2期243-246,共4页Nuclear Electronics & Detection Technology

基　　金：国家自然科学基金资助项目(10505020)

摘　　要：为实现嵌入式CPU和两路数据采集系统之间的长距离高速通信,利用FPGA将嵌入式CPU的MII(介质无关接口)扩展成两个40Mbps的非标准数据率MII,FPGA通过这两个MII和长距离以太网收发器通信,接收和汇聚来自220米以外的数据采集系统的数据,数据采集系统的最高数据率为24Mbps,这些数据最后通过嵌入式CPU的MII发送给CPU。全部逻辑设计在Xilinx的XC3S100E上实现,通过基于S3C4510B的测试平台测试验证其正确性,在实际使用中效果良好。Communication interface between embedded CPU and two channel data acquisition systems was implemented based on FPGA. These two channel data acquisition systems were 220 meters away and the peak data rate was 24Mbps per channel FPGA was used to expand embedded CPU＇s MII（Media Inde- pendent Interface） into two MII which worked at a nonstandard bit rate （40Mbps）, communicated with two long range Ethernet transceiver and received data from these two channel data acquisition systems. The data was merged by FPGA and transmitted to embedded CPU through CPU＇s MII. The whole logic design was implemented in Xilinx＇s XC3S100E device, verified on the hardware test platform based on an ARM ehip（S3CA510B） and worked well in practice.

关 键 词：FPGA 嵌入式CPU MII 长距离以太网 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]