一种Montgomery模乘算法硬件结构  

Hardware Architecture for the Montgomery Multiplication Algorithm

作　　者：王缔郦[1] 白国强[1] 陈弘毅[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学与计算机》2010年第5期1-4,共4页Microelectronics & Computer

摘　　要：基于二进制多字Montgomery模乘算法,提出了一种参数可灵活配置的规则的脉动阵列硬件结构,并使用此结构在FPGA上实现了不同位宽的Montgomery模乘算法.该结构成功地在不增加额外电路或运行周期的情况下,将脉动阵列的关键路径限制在运算单元内部的加法器中.硬件实现结果表明,该结构具有更高的电路频率、更少的电路面积消耗及算法运算时间.In this paper, regular and flexible hardware architecture based on the systolic array for implementing the multiple-word radix-2 Montgomery multiplication algorithm is proposed, and it has been used to implement the algorithm in FPGA for different bit-widths. The architecture successfully limits the critical path of the systolic array to the critical path of the adder in a processing element, without any additional circuits or clock cycles needed. According to the hardware implement results, the proposed architecture has higher frequency, less latency and less area.

关 键 词：RSA Montgomery模乘算法 硬件 脉动阵列 

分 类 号：TN4[电子电信—微电子学与固体电子学]