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机构地区:[1]Institute of RF-& OE-ICs,Southeast University [2]Engineering Research Center of RF-ICs & RF-Systems,Ministry of Education,Southeast University
出 处:《Journal of Semiconductors》2010年第5期85-89,共5页半导体学报(英文版)
基 金:supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7);the Science and Technology Program of Zhejiang Province,China(No.2008C16017).
摘 要:A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm^2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm^2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.
关 键 词:frequency divider dual-modulus prescaler pulse-swallow frequency synthesizer
分 类 号:TN772[电子电信—电路与系统] TN912.3
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