基于FPGA的单精度浮点数乘法器设计  

An FPGA implementation of single precision floating-point multiplier

作　　者：旷捷[1] 毛雪莹[1] 彭俊淇[1] 黄启俊[1] 常胜[1] 

机构地区：[1]武汉大学物理科学与技术学院,湖北武汉430072

出　　处：《电子技术应用》2010年第5期17-19,共3页Application of Electronic Technique

摘　　要：设计了一个基于FPGA的单精度浮点数乘法器。设计中采用改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构,并提出对Wallace树产生的2个伪和采用部分相加的方式,提高了乘法器的运算速度;加入对特殊值的处理模块,完善了乘法器的功能。本设计在AlteraDE2开发板上进行了验证。An FPGA implementation of single precision floating-point muhiplier is introduced in this thesis. With the usage of modified redundant Booth3 with bias and leapfrog Wallace tree, and the application of partial addition in fixed-point multiplication, the efficiency of the 5-stage multiplier is promoted. Moreover, a module dealing with special values is introduced to perfect the function of the multiplier. The verification of the multiplier is accomplished on Ahera DE2.

关 键 词：改进的带偏移量的冗余Booth3算法 跳跃式Wallace树 单精度浮点数乘法器 FPGA 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]