基于DDS+PLL技术频率合成器的设计与实现  

Design and implementation of frequency synthesizer based on DDS & PLL

作　　者：陈科[1] 叶建芳[1] 马三涵[1] 

机构地区：[1]东华大学信息科学与技术学院通信与电子工程系,上海201620

出　　处：《国外电子测量技术》2010年第4期43-47,共5页Foreign Electronic Measurement Technology

摘　　要：本文介绍了DDS+PLL方式实现频率合成的基本原理和技术优势。根据GSM-1900系统对频率源的要求,提出了一种基于DDS+PLL结构频率合成器的硬件电路设计方案。借助于EDA仿真软件ADS、ADISimPLL完成了频率合成器中关键模块参数的确定,并对系统性能进行了仿真分析,最后运用AD9851、ADF4113等芯片完成了频率合成器的硬件实现,测量结果表明该频率合成器达到了设计指标,系统性能良好。A frequency synthesizer based on DDS＋PLL framework is presented,and its basic principles and technological advantages are described in detail as well.According to the requirement of GSM-1900 system,this paper proposes a hardware design of a frequency synthesizer using DDS and PLL technology.By the aid of EDA software ADS and ADISim-PLL, parameters of key modules are determined.Based on the outcome of simulation and analysis,the frequency synthesizer has been implemented with DDS chip AD9851 and Phase-lock chip ADF4113.Test result show that the frequency synthesizer achieves the design objective and the system has good performance.

关 键 词：DDS PLL 频率合成 

分 类 号：TN743[电子电信—电路与系统]