组合电路门时滞故障的可测性分析  

Analysis of Gate Delay Fault's Testabilityin Combinational Circuits

作　　者：王勇[1] 

机构地区：[1]电子科技大学CAT室

出　　处：《电子科技大学学报》1999年第1期58-61,共4页Journal of University of Electronic Science and Technology of China

摘　　要：根据时滞故障测试的特点，定义了一种门时滞故障的可测性测度（即上升沿和下降沿门时滞故障的可控制性和可观测性），并提出了相应的计算方法，为基于门时滞故障的电路可测性论计提供了理论依据。According to the feature of the testing for gate delay faults, the testability measures of the gatedelay faults are defined (the controllability and the observability of the gate delay faults in the rising or fallingtransition), and the method of computing these two measures are presented, which provides the quantitativecriteria of design for testability of the gate delay faults.

关 键 词：门时滞故障 可测性测度 可控制性 可观测性 VLSI 

分 类 号：TN470.7[电子电信—微电子学与固体电子学]