DLMS高速自适应滤波器的FPGA实现  

Implementation of DLMS High Speed Adaptive Filter in FPGA

作　　者：杨东[1] 王建业[1] 

机构地区：[1]空军工程大学导弹学院,陕西三原713800

出　　处：《电声技术》2010年第5期41-43,共3页Audio Engineering

摘　　要：在分析传统自适应滤波算法的基础上,针对自适应滤波器的硬件实现,采用一种适合FPGA实现的DLMS算法。使用VHDL语言完成设计,仿真实验验证了设计的正确性,经过编译和布局布线后对改进算法和传统算法进行了比较,结果表明改进算法在增加硬件消耗较少的情况下有效提高了系统工作频率。Based on the analyse of traditional adaptive filter algorithm, an DLMS algorithm using FPGA is used aimed at the implementation of adaptive filter. The VHDL language is used to accomplish the design. The improved algorithmic with traditional algorithmic are compared after compiled and wired. The simulation experiments show that the improved algorithm can work in higher frequency with a low hardware cost increase.

关 键 词：自适应滤波器 DLMS算法 FPGA 

分 类 号：TN713[电子电信—电路与系统]