基于FPGA的H.264帧内预测算法研究  

Study of H.264 Intra Prediction Algorithm Based on FPGA

作　　者：于小燕[1] 赵不贿[1] 郑博[1] 吴长江[1] 

机构地区：[1]江苏大学电气信息工程学院,江苏镇江212013

出　　处：《电视技术》2010年第5期40-43,56,共5页Video Engineering

基　　金：江苏省科技成果转化专项资金(BA2009001)

摘　　要：采用FPGA以并行处理方式实现了H.264的帧内预测。系统被划分成多个功能模块,采用层次化、模块化的设计思想,并采用流水线结构和乒乓操作来提高系统的并行性、运行速度和总线利用率。所有模块用Verilog语言设计,由Modelsim仿真和集成开发环境ISE9.1综合,最后通过Spartan3E开发板进行实验验证。仿真结果表明,该设计能够很好地满足实时性要求。A parallel implementation based on FPGA is proposed to realize H.264 intra prediction in this paper. In order to reduce the complexity of hardware implementation, the design is divided into some function modules by using the design approach of hiberarchy and modularization. Pipeline and ping-pong operation are used to increase the parallelity, speed and bus utilization rate of the system. All of the modules are designed using Verilog, simulated in Modelsim, synthesized in ISE9. 1 and verified to work in Xilinx Spartan3E board. The simulation results indicate that the design meets the real-time requirement.

关 键 词：视频编码 帧内预测 H.264 现场可编程门阵列 

分 类 号：TN919.81[电子电信—通信与信息系统]