用于FPGA快速重构的配置电路  

Configuration Circuit Used for FPGA Fast Reconfiguration

作　　者：谢婧[1] 王亚斌[1] 来金梅[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2010年第2期165-170,176,共7页Journal of Fudan University：Natural Science

基　　金：国家自然科学基金(60876015);国家高技术研究发展计划("863"计划)(2007AA01Z285)资助项目

摘　　要：提出了一种适于FPGA芯片的快速重构配置电路,并在FDP2009Ⅱ-SOPCFPGA芯片里设计实现.其主要特点为:配置电路使芯片最小配置单元由Xilinx的Spartan和Virtex系列芯片的一帧变为32 bit,减少了重配置传送的配置数据,缩短了芯片重构时间.FDP2009-Ⅱ-SOPC FPGA采用SMIC0.13μm一层多晶八层金属工艺设计,芯片总面积为4.5 mm×6.3 mm,配置电路面积为1.7 mm^2.版图后仿真结果表明,配置电路能够正确的完成数据重配置功能,芯片重构时间是Xilinx公司的Virtex系列相同规模FPGA芯片的34%左右.A configuration architecture of FPGA suitable for fast reconfiguration is proposed and implemented for FDP2009-Ⅱ-SOPC FPGA（Fudan Programmable device 2009-Ⅱ-SOPC）. This circuit makes a 32-bit memory cell of FPGA addressable. The smallest configuration in this circuit is 32 bit while that of Virtex Series FPGA is one frame. The improved configuration circuit could make reconfiguration bitstream smaller and shorten recon- figuration time of the system. FDP2009-Ⅱ-SOPC FPGA is manufactured with SMIC 0. 13μm CMOS 1P8M process. The die size of FDP2009-Ⅱ-SOPC FPGA is about 4. 5 mm× 6.3 mm and the area of this configuration circuit is about 1.7 mm2. The post layout simulation shows that this configuration circuit of FDP2009-Ⅱ-SOPC FPGA could work correctly and efficiently and the configuration time is about 34 % of that of Xilinx Virtex Ⅱ series FPC-A with the similar size.

关 键 词：现场可编程门阵列 配置电路 可重构 可寻址配置寄存器 

分 类 号：TN402[电子电信—微电子学与固体电子学]