用于小LSB并行ADC的新型节约面积的预放大器链设计方法(英文)  

A Novel Design Method for Area-Efficient Preamplifier Chain of Very-Small-LSB Flash ADC

作　　者：牛祺[1] 吕昌辉[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2010年第2期229-235,共7页Journal of Fudan University：Natural Science

摘　　要：伴随高精度电源系统的发展,数字电压调整模块(DVRM)需要高速,高精度的模数转换器.为此,提出了一种新型预放大器链设计方法,能够获得非常小的LSB.该方法优化了预放大器输入管的尺寸,在保证足够小的失调电压的前提下,使各级输入管面积总和最小.为验证该优化方法,结合电阻均衡技术,构造了一个3级结构flash型ADC.与一般设计相比,输入管总面积减少了57%.每个LSB为3.125 mV,直接转换精度3.5 bit,得益于窗口结构,在满度输入范围内等效精度为8 bit,采样率为224 Msample/s.Because of the development of high precision power systems, digital voltage-regulator-module （DVRM） needs high speed and high precision analog-to-digital converters （ADC）. A novel design method is proposed for the flash ADC＇s preamplifier chain with the very small least significant bit （LSB）, used for DVRM applications, which makes the total area of all input transistors minimum while keeping the offset small enough. An experimental flash ADC with a 3-stage pre-amplifier chain is built up to validate the proposed design method, together employing other techniques such as resistor averaging. The total input transistors＇ area is reduced by 57 compared to the general design. The direct conversion resolution is 3.5 bit with 3.125 mV/LSB and the effective resolution is 8 bit over the full input range, taking the advantage of the window structure. The ADC can operate up to 224 M sample/s.

关 键 词：窗口型flash ADC 面积优化 高精度 数字电压调整模块 电阻均衡 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]