基于FPGA的Turbo码译码器设计与实现  

Design and Implementation of Turbo Decoder Based on FPGA

作　　者：薛礼妮[1] 刘展威[2] 

机构地区：[1]华北电力大学电气与电子工程学院,北京102206 [2]石家庄铁道学院计算机与信息工程学院,石家庄050043

出　　处：《太原理工大学学报》2010年第3期260-264,共5页Journal of Taiyuan University of Technology

摘　　要：对Turbo码的Log-MAP译码算法进行了研究,引入滑动窗技术对Log-MAP译码算法进行了优化,并设计了适合硬件实现的流水线结构的译码器。结合3G标准规定的数据速率,对译码器和交织器进行硬件电路的设计和FPGA实现。仿真结果表明所设计的电路在译码性能和延迟方面满足实际要求,具有一定的实用价值。This paper researched and optimized the Log-MAP decoding algorithm of Turbo code through introducing the sliding window technique, and designed a pile line structure that cound be easily realized with hardware. A pile line structure of Turbo decoder and interweave component with hardware circuit were realized by using FPGA technique according to specified data rate of the 3G criterion. The result indicates that the designed circuit can satisfy need in decoding performance and delay, therefore, will have practical value.

关 键 词：TURBO码 LOG-MAP算法 滑动窗 FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]