嵌入式USB2.0主机控制器内核SIE的设计  

Design of Serial Interface Engine of Host Controller Based on USB 2.0 Protocol

作　　者：黄君凯[1] 黎永健[1] 张爱丽[1] 

机构地区：[1]暨南大学电子工程系,广州510632

出　　处：《微计算机信息》2010年第17期12-14,共3页Control & Automation

摘　　要：完成了一种可应用于嵌入式USB2.0主机控制器的串行接口引擎SIE的IP软核设计。讨论了解码、编码、拆包、组包、CRC检验、数字时钟提取和总线计时检测等7个模块的设计,并对设计结果进行了综合及时序仿真验证。结果表明,所设计的SIEIP核在功能和时序上满足USB2.0协议要求。This paper has achieved the IP soft core designing of serial interface engine （SIE）, which applied in embedded USB2.0 host controller. The design of seven modules, decoding, coding,disassemble packet, assemble packet, CRC verification, digital clock recovery and bus time counter is discussed in detail, then timing simulated, complied, synthesized and fitted into FPGA. The results of simulation and verification show that the SIE IP core meets USB2.0 protocol in function and timing.

关 键 词：USB2.0 主机控制器 串行接口引擎(SIE) IP核 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]