基于FPGA的SOPC的图像采集模块设计  

The image gathering module design based on SOPC of FPGA

作　　者：詹毕旺[1] 

机构地区：[1]上海理工大学,200093

出　　处：《微计算机信息》2010年第17期134-136,共3页Control & Automation

摘　　要：在低速的数据采集系统中,往往采用单片机或者DSP进行控制;而图像采集通常由图像采集卡和计算机共同完成,整个图像采集系统功耗大,体积大。针对这些问题,提出了一种基于FPGA的SOPC的图像采集模块的设计,主要的控制逻辑由硬件完成,速度快、成本低和灵活性强。采用了可定制嵌入式系统NIOS为处理器核心,配以高速CMOS器件的驱动器和SRAM控制器,形成了一个小型化,可方便升级的可编程图像采集系统。it is widely used that MCU or DSP used for control in the low speed data acquisition system. Image gathering system usually consists of the image garhering card and the computer ,and moreover the entir image gathering system too big to save power,and the volume is too big.In view of these questions,l proposed the design of the image gathering module based on SOPC of FPGA.the main control logic compehes by the hardware,and its speed is quick and flexible,cost is low.l used the NIOS processor core which is custom-made embedded to design the high speed COMS component＇s driver, the SRAM controller,forming a miniaturization and facilitating the programmable image gathering system promoted.

关 键 词：NIOS处理器 SOPC系统 可编程 

分 类 号：TN495[电子电信—微电子学与固体电子学]