存储器行缓冲区命中预测研究  

Research on Row Buffer Hit Prediction for Memory Access

作　　者：王得利[1] 高德远[1] 王党辉[1] 孙华锦[1] 

机构地区：[1]西北工业大学计算机学院,西安710072

出　　处：《计算机科学》2010年第6期297-302,共6页Computer Science

基　　金：国家自然科学基金项目(60573107);国家自然科学基金项目(60573143);国家863项目(2007aa010402)资助

摘　　要：存储系统已经成为提高计算机系统性能的一个瓶颈。现利用DRAM存储器的访问特性来减少存储器访问操作的平均延迟。首先对存储器行缓冲区的控制策略进行研究,提出了读写分离式页模式预测器,并提出了双饱和计数器预测器和2级预测器等两种预测器方案;然后以SimpleScalar搭建的仿真平台对提出的预测方案进行了性能评估。结果显示,与缓冲区"关"策略相比,平均访问延迟减少了26%,IPC平均提高了4.3%;与缓冲区"开"策略相比,平均访问延迟减少了19.6%,IPC平均提高了2.5%。Memory system becomes a bottle-neck for the overall computer system performance. This paper reduced the average memory access latency using the characteristics of DRAM. Firstly, the control strategy for memory row buffer was studied. Secondly, a Read and Write Separated Predictor （RWS） for page mode prediction was proposed, a two saturated counter and a two level predictor to realize RWS were also proposed. Finally, a simulation platform based on SimpleScalar was constructed to evaluate the proposed predictors. The result shows that compared with CLOSE strategy, the average memory access latency is reduced about 26 %, the average IPC speedup is about 4. 3%. It is also shown that the average memory access latency is reduced about 19. 6%, the average IPC speedup is about 2. 5% Compared with OPEN strategy.

关 键 词：存储系统 行缓冲区 页模式预测 读写分离 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]