基于FPGA的乘法器设计和实现  

Design and Implementation of Multiplier Using FPGA

作　　者：蒋俊华[1] 王蓓[1] 张婷[1] 李宗惠[1] 

机构地区：[1]河南大学物理与电子学院,河南开封475001

出　　处：《河南机电高等专科学校学报》2010年第2期23-25,64,共4页Journal of Henan Mechanical and Electrical Engineering College

摘　　要：乘法器是数字信号处理领域的基本逻辑部件,应用广泛。用Verilog硬件描述语言设计了加法树乘法器、查找表乘法器和Booth乘法器,在Modelsim软件环境下进行了仿真,在QuartusII开发平台上基于Stratix器件对这三种方案进行了综合验证,并对结果进行了分析和比较。The multiplier is widely used in the digital signal processing field as a bASIC logic component. The text has designed three kinds of multplier by verilog hardware description language, they are addition device tree multiplier, look up table multiplier and booth multiplier. The simulation -synthesizing is carried out in stratix device by quartusII software , and we analyze and compare the result

关 键 词：数字信号处理 乘法器 Stratix器件 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]