芯片设计中的功耗估计与优化技术  

The technique of power estimation and optimization in ASIC design

作　　者：于立波[1] 

机构地区：[1]电子科技大学微电子与固体电子学院,成都611731

出　　处：《中国集成电路》2010年第6期37-43,共7页China lntegrated Circuit

摘　　要：在芯片设计中,低功耗一直是一个重要的目标,受到封装、供电、散热的约束,并且最大功耗限制越来越严格。在本文中,首先讨论了芯片中的功耗来源。接着,阐述了在设计过程初期可以采用的几项可以降低功耗的技巧。本文提出的方法用于架构设计和前段设计的初期,如功耗估计、低功耗架构优化和时钟门控等。Low-power design is an important goal for ASIC design, where constraints on packaging, power supply and heat dissipation continue to add increasingly strict limits to the maximum amount of power. In this paper, we discuss the sources of power consumption in modem chips. Then, we present several design strategies in the design process to reduce power consumption. Our methods target the architectural and phases, such as power-estimation, architecture optimization for low power and clock gating.

关 键 词：低功耗设计 功耗估计 功耗优化 时钟门控 

分 类 号：TN402[电子电信—微电子学与固体电子学]