基于绝热逻辑的低功耗乘法器电路设计  

Low-power Multiplier Design Based on Adiabatic Logic

作　　者：任国燕[1] 

机构地区：[1]重庆科技学院电工电子教研室,重庆401331

出　　处：《现代电子技术》2010年第12期8-9,12,共3页Modern Electronics Technique

摘　　要：基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。Energy recover logic （ERL） based on adiabatic switching theory can greatly reduce the power consumption com- pared with traditional static CMOS logic. An energy recover logic using a single-phase sinusoidal power clock is introduced. A two-bit multiplier was designed and simulated for both ERL and static CMOS logic, the performance of the circuits was com- pared. The results show that the multiplier designed by energy recover logic can shorten the power consumption.

关 键 词：能量回收逻辑 绝热电路 低功耗 乘法器 

分 类 号：TN79[电子电信—电路与系统]