A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors  

作　　者：庄敏宏 张家伟 史德智 黄全洲 王志良 张胜良 

机构地区：[1]Department of Electronic Engineering National Taiwan University of Science and Technology [2]Department of Electronic Engineering Ming-Chi University of Technology

出　　处：《Journal of Semiconductors》2010年第6期39-43,共5页半导体学报（英文版）

基　　金：Project supported by the National Science Council(NSC),Taiwan,China(No.NSC 97-2221-E-011-136).

摘　　要：A process simplification scheme for fabricating CMOS poly-Si thin-film transistors（TFTs） has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer（LAITS）.By this LATITS scheme,a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus（or boron） dopant through the spacer,and then the n~＋-source/drain（n~＋-S/D）（or p~＋-S/D） region is formed via using the same photo-mask layer during CMOS integration.For both n-TFT and p-TFT devices,as compared to the sample with conventional single n~＋-S/D（or p~＋-S/D） structure,the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field.In addition,the resultant on-state currents only show slight degradation for the LATITS scheme.As a result,by the LATITS scheme,CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.A process simplification scheme for fabricating CMOS poly-Si thin-film transistors（TFTs） has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer（LAITS）.By this LATITS scheme,a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus（or boron） dopant through the spacer,and then the n~＋-source/drain（n~＋-S/D）（or p~＋-S/D） region is formed via using the same photo-mask layer during CMOS integration.For both n-TFT and p-TFT devices,as compared to the sample with conventional single n~＋-S/D（or p~＋-S/D） structure,the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field.In addition,the resultant on-state currents only show slight degradation for the LATITS scheme.As a result,by the LATITS scheme,CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.

关 键 词：polycrystalline-Si thin-film transistor process simplification large-angle-tilt-implantation 

分 类 号：TN321.5[电子电信—物理电子学] TN432