A low-power CMOS frequency synthesizer for GPS receivers  

作　　者：于云丰 乐建连 肖时茂 庄海孝 马成炎 叶甜春 

机构地区：[1]Institute of Microelectronics Chinese Academy of Sciences [2]Hangzhou Zhongke Microelectronics Co.Ltd.

出　　处：《Journal of Semiconductors》2010年第6期137-141,共5页半导体学报（英文版）

基　　金：Project supported by the National Municipal Sci-Tech Project of China(No.2009ZX01031-002-008);the National High Technology Research and Development Program of China(No.2007AA12Z344).

摘　　要：A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm;.A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm^2.

关 键 词：frequency synthesizer GPS CMOS PLL source-coupled logic prescaler 

分 类 号：TN74[电子电信—电路与系统] P228.4[天文地球—大地测量学与测量工程]