版图面积受限POR电路中复位延迟问题的研究  

Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit

作　　者：屈小钢[1,2] 杨海钢[1] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《电子与信息学报》2010年第6期1389-1394,共6页Journal of Electronics & Information Technology

摘　　要：针对上电复位电路中实现毫秒级复位时间的电阻和电容所需面积过大的问题,该文给出了一种基于指数时间扩展技术的面积有效的延时电路。该电路利用环形振荡器产生信号的周期作为参考单位延时,通过异步分频实现增大的指数倍的延时,能在节省芯片面积的情况下实现毫秒级延时,在上电复位电路中实现足够长的复位时间。同时,该文给出了SMIC 0.18μm工艺下设计的SPICE仿真和实验测试结果。实现延迟时间0.91ms和54.9ms时,电路版图面积分别约为172μm×75μm和172μm×95μm。与通常的RC方法相比,实现相同的延时至少各节省约82.8%和97%的面积。To solve the problem of an excessive area required to implement milliseconds reset time with resistance and capacitance in POR（Power-On Reset） circuit,an area-efficiency delay circuit based on an exponential time-extending technique is proposed in this paper.The circuit utilizes asynchronous frequency division to increase delay exponentially,using the period of signal which ring oscillator generates as a reference delay unit and is capable of implementing milliseconds delay for minimum silicon area.It is used to generate a long enough reset time in the POR circuit.To verify the technique,the circuit is designed and fabricated in the SMIC 0.18 μm process.According to the measured results,the circuit typically achieves 0.91 ms delay with an area of 172 μm×75 μm and 54.9 ms delay with an area of 172 μm×95 μm.As compared with RC method,the circuit can respectively save at least 82.8% and 97% layout area for implementing the same delays.

关 键 词：VLSI ASIC 可编程逻辑器件 延时电路 上电复位电路 

分 类 号：TN402[电子电信—微电子学与固体电子学]